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sja1000.h File Reference
#include <sys/time.h>
#include "utils/common.h"
#include "utils/timestamp.h"
#include "delay.h"
Include dependency graph for sja1000.h:
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Go to the source code of this file.

Classes

union  frame
 
struct  canregs
 
struct  CanStatusPar
 
struct  inode
 
struct  _instance_data
 
struct  file
 

Macros

#define INCLUDE_CAN_SJA1000_H_
 
#define SJA1000_MAP_SIZE   128
 
#define CAN_RANGE   0x20 /* default: 32 registers */
 
#define CAN_SLEEP_MODE   0x10
 
#define CAN_ACC_FILT_MASK   0x08
 
#define CAN_SELF_TEST_MODE   0x04
 
#define CAN_LISTEN_ONLY_MODE   0x02
 
#define CAN_RESET_REQUEST   0x01
 
#define CAN_MODE_DEF   CAN_ACC_FILT_MASK
 
#define CAN_ERROR_BUSOFF_INT_ENABLE   (1<<7)
 
#define CAN_ARBITR_LOST_INT_ENABLE   (1<<6)
 
#define CAN_ERROR_PASSIVE_INT_ENABLE   (1<<5)
 
#define CAN_WAKEUP_INT_ENABLE   (1<<4)
 
#define CAN_OVERRUN_INT_ENABLE   (1<<3)
 
#define CAN_ERROR_INT_ENABLE   (1<<2)
 
#define CAN_TRANSMIT_INT_ENABLE   (1<<1)
 
#define CAN_RECEIVE_INT_ENABLE   (1<<0)
 
#define CAN_EFF   0x80
 
#define CAN_SFF   0x00
 
#define CAN_GOTO_SLEEP   (1<<4)
 
#define CAN_CLEAR_OVERRUN_STATUS   (1<<3)
 
#define CAN_RELEASE_RECEIVE_BUFFER   (1<<2)
 
#define CAN_ABORT_TRANSMISSION   (1<<1)
 
#define CAN_TRANSMISSION_REQUEST   (1<<0)
 
#define CAN_BUS_STATUS   (1<<7)
 
#define CAN_ERROR_STATUS   (1<<6)
 
#define CAN_TRANSMIT_STATUS   (1<<5)
 
#define CAN_RECEIVE_STATUS   (1<<4)
 
#define CAN_TRANSMISSION_COMPLETE_STATUS   (1<<3)
 
#define CAN_TRANSMIT_BUFFER_ACCESS   (1<<2)
 
#define CAN_DATA_OVERRUN   (1<<1)
 
#define CAN_RECEIVE_BUFFER_STATUS   (1<<0)
 
#define CAN_WAKEUP_INT   (1<<4)
 
#define CAN_OVERRUN_INT   (1<<3)
 
#define CAN_ERROR_INT   (1<<2)
 
#define CAN_TRANSMIT_INT   (1<<1)
 
#define CAN_RECEIVE_INT   (1<<0)
 
#define CAN_OCTP1   (1<<7)
 
#define CAN_OCTN1   (1<<6)
 
#define CAN_OCPOL1   (1<<5)
 
#define CAN_OCTP0   (1<<4)
 
#define CAN_OCTN0   (1<<3)
 
#define CAN_OCPOL0   (1<<2)
 
#define CAN_OCMODE1   (1<<1)
 
#define CAN_OCMODE0   (1<<0)
 
#define CAN_MODE_BASICCAN   (0x00)
 
#define CAN_MODE_PELICAN   (0xC0)
 
#define CAN_MODE_CLK1   (0x07)
 
#define CAN_MODE_CLK2   (0x00)
 
#define CAN_MODE_CLK   CAN_MODE_CLK2
 
#define CAN_RTR   (1<<6)
 
#define CAN_TIM0_10K   49
 
#define CAN_TIM1_10K   0x1c
 
#define CAN_TIM0_20K   24
 
#define CAN_TIM1_20K   0x1c
 
#define CAN_TIM0_40K   0x89
 
#define CAN_TIM1_40K   0xEB
 
#define CAN_TIM0_50K   9
 
#define CAN_TIM1_50K   0x1c
 
#define CAN_TIM0_100K   4
 
#define CAN_TIM1_100K   0x1c
 
#define CAN_TIM0_125K   3
 
#define CAN_TIM1_125K   0x1c
 
#define CAN_TIM0_250K   1
 
#define CAN_TIM1_250K   0x1c
 
#define CAN_TIM0_500K   0
 
#define CAN_TIM1_500K   0x1c
 
#define CAN_TIM0_800K   0
 
#define CAN_TIM1_800K   0x16
 
#define CAN_TIM0_1000K   0
 
#define CAN_TIM1_1000K   0x14
 
#define MAX_CHANNELS   1
 
#define MY_CHANNEL   0
 
#define DBGprint(ms, ar)   { }
 
#define DBGin()   { }
 
#define DBGout()   { }
 
#define DEBUG_TTY(n, args...)
 
#define MSG_ACTIVE   (0)
 
#define MSG_BASE   (0)
 
#define MSG_RTR   (1<<0)
 
#define MSG_OVR   (1<<1)
 
#define MSG_EXT   (1<<2)
 
#define MSG_SELF   (1<<3)
 
#define MSG_PASSIVE   (1<<4)
 
#define MSG_BUSOFF   (1<<5)
 
#define MSG_WARNING   (1<<6)
 
#define MSG_BOVR   (1<<7)
 
#define MSG_ERR_MASK   (MSG_OVR+MSG_PASSIVE+MSG_BUSOFF+MSG_BOVR+MSG_WARNING)
 
#define CAN_SFF_MASK   0x000007FFU
 
#define CAN_EFF_MASK   0x1FFFFFFFU
 
#define CANDRIVERERROR   0xFFFFFFFFul
 
#define LINUX_VERSION_CODE   1
 
#define KERNEL_VERSION(X, Y, Z)   0
 
#define IRQ_NONE   0
 
#define IRQ_HANDLED   1
 
#define IRQ_RETVAL(x)   (x)
 
#define CANin(bd, adr)   can_read_reg(&can_base_addr->adr)
 
#define CANout(bd, adr, v)   can_write_reg(&can_base_addr->adr, v)
 
#define CANset(bd, adr, m)   can_set_reg(&can_base_addr->adr, m)
 
#define CANreset(bd, adr, m)   can_reset_reg(&can_base_addr->adr, m)
 
#define R_OFF   1
 

Typedefs

typedef struct CanStatusPar CanStatusPar_t
 
typedef int irqreturn_t
 

Functions

struct canregs __attribute__ ((packed)) canregs_t
 

Variables

BYTE canmode
 
BYTE cancmd
 
BYTE canstat
 
BYTE canirq
 
BYTE canirq_enable
 
BYTE reserved1
 
BYTE cantim0
 
BYTE cantim1
 
BYTE canoutc
 
BYTE cantest
 
BYTE reserved2
 
BYTE arbitrationlost
 
BYTE errorcode
 
BYTE errorwarninglimit
 
BYTE rxerror
 
BYTE txerror
 
BYTE frameinfo
 
union frame frame
 
BYTE reserved3
 
BYTE canrxbufferadr
 
BYTE canclk
 
unsigned int dbgMask
 
canregs_t * can_base_addr
 

Detailed Description

sja1000.h

This includes device-dependent CAN definitions for the Phillips SJA 1000 driver. Assumes board is memory mapped at address given during initialization.

Author
Abdul Rahman Kreidieh
Version
1.0.0
Date
April 6, 2018

Macro Definition Documentation

◆ CAN_ABORT_TRANSMISSION

#define CAN_ABORT_TRANSMISSION   (1<<1)

bit 1 in Command Register (see include/can/sja1000.h for details)

◆ CAN_ACC_FILT_MASK

#define CAN_ACC_FILT_MASK   0x08

Acceptance Filter Mask

◆ CAN_ARBITR_LOST_INT_ENABLE

#define CAN_ARBITR_LOST_INT_ENABLE   (1<<6)

bit 6 in Interrupt Enable Register (see include/can/sja1000.h for details)

◆ CAN_BUS_STATUS

#define CAN_BUS_STATUS   (1<<7)

bit 7 in Status Register (see include/can/sja1000.h for details)

◆ CAN_CLEAR_OVERRUN_STATUS

#define CAN_CLEAR_OVERRUN_STATUS   (1<<3)

bit 3 in Command Register (see include/can/sja1000.h for details)

◆ CAN_DATA_OVERRUN

#define CAN_DATA_OVERRUN   (1<<1)

bit 1 in Status Register (see include/can/sja1000.h for details)

◆ CAN_EFF

#define CAN_EFF   0x80

extended frame

◆ CAN_EFF_MASK

#define CAN_EFF_MASK   0x1FFFFFFFU

Extended Frame Format (EFF)

◆ CAN_ERROR_BUSOFF_INT_ENABLE

#define CAN_ERROR_BUSOFF_INT_ENABLE   (1<<7)

bit 7 in Interrupt Enable Register (see include/can/sja1000.h for details)

◆ CAN_ERROR_INT

#define CAN_ERROR_INT   (1<<2)

bit 2 in Interrupt Register (see include/can/sja1000.h for details)

◆ CAN_ERROR_INT_ENABLE

#define CAN_ERROR_INT_ENABLE   (1<<2)

bit 2 in Interrupt Enable Register (see include/can/sja1000.h for details)

◆ CAN_ERROR_PASSIVE_INT_ENABLE

#define CAN_ERROR_PASSIVE_INT_ENABLE   (1<<5)

bit 5 in Interrupt Enable Register (see include/can/sja1000.h for details)

◆ CAN_ERROR_STATUS

#define CAN_ERROR_STATUS   (1<<6)

bit 6 in Status Register (see include/can/sja1000.h for details)

◆ CAN_GOTO_SLEEP

#define CAN_GOTO_SLEEP   (1<<4)

bit 4 in Command Register (see include/can/sja1000.h for details)

◆ CAN_LISTEN_ONLY_MODE

#define CAN_LISTEN_ONLY_MODE   0x02

Listen only mode

◆ CAN_MODE_BASICCAN

#define CAN_MODE_BASICCAN   (0x00)

Specifies BasicCAN Mode

◆ CAN_MODE_CLK

#define CAN_MODE_CLK   CAN_MODE_CLK2

On the Janus-MM board the correct CLKout is Fclk/2

◆ CAN_MODE_CLK1

#define CAN_MODE_CLK1   (0x07)

CLK-out = Fclk

◆ CAN_MODE_CLK2

#define CAN_MODE_CLK2   (0x00)

CLK-out = Fclk/2

◆ CAN_MODE_DEF

#define CAN_MODE_DEF   CAN_ACC_FILT_MASK

Default ModeRegister Value

◆ CAN_MODE_PELICAN

#define CAN_MODE_PELICAN   (0xC0)

Specifies Pelican Mode

◆ CAN_OCMODE0

#define CAN_OCMODE0   (1<<0)

bit 1 in Output Control Register (see include/can/sja1000.h for details)

◆ CAN_OCMODE1

#define CAN_OCMODE1   (1<<1)

bit 2 in Output Control Register (see include/can/sja1000.h for details)

◆ CAN_OCPOL0

#define CAN_OCPOL0   (1<<2)

bit 3 in Output Control Register (see include/can/sja1000.h for details)

◆ CAN_OCPOL1

#define CAN_OCPOL1   (1<<5)

bit 6 in Output Control Register (see include/can/sja1000.h for details)

◆ CAN_OCTN0

#define CAN_OCTN0   (1<<3)

bit 4 in Output Control Register (see include/can/sja1000.h for details)

◆ CAN_OCTN1

#define CAN_OCTN1   (1<<6)

bit 7 in Output Control Register (see include/can/sja1000.h for details)

◆ CAN_OCTP0

#define CAN_OCTP0   (1<<4)

bit 5 in Output Control Register (see include/can/sja1000.h for details)

◆ CAN_OCTP1

#define CAN_OCTP1   (1<<7)

bit 8 in Output Control Register (see include/can/sja1000.h for details)

◆ CAN_OVERRUN_INT

#define CAN_OVERRUN_INT   (1<<3)

bit 3 in Interrupt Register (see include/can/sja1000.h for details)

◆ CAN_OVERRUN_INT_ENABLE

#define CAN_OVERRUN_INT_ENABLE   (1<<3)

bit 3 in Interrupt Enable Register (see include/can/sja1000.h for details)

◆ CAN_RECEIVE_BUFFER_STATUS

#define CAN_RECEIVE_BUFFER_STATUS   (1<<0)

bit 0 in Status Register (see include/can/sja1000.h for details)

◆ CAN_RECEIVE_INT

#define CAN_RECEIVE_INT   (1<<0)

bit 0 in Interrupt Register (see include/can/sja1000.h for details)

◆ CAN_RECEIVE_INT_ENABLE

#define CAN_RECEIVE_INT_ENABLE   (1<<0)

bit 0 in Interrupt Enable Register (see include/can/sja1000.h for details)

◆ CAN_RECEIVE_STATUS

#define CAN_RECEIVE_STATUS   (1<<4)

bit 4 in Status Register (see include/can/sja1000.h for details)

◆ CAN_RELEASE_RECEIVE_BUFFER

#define CAN_RELEASE_RECEIVE_BUFFER   (1<<2)

bit 2 in Command Register (see include/can/sja1000.h for details)

◆ CAN_RESET_REQUEST

#define CAN_RESET_REQUEST   0x01

Reset mode

◆ CAN_RTR

#define CAN_RTR   (1<<6)

— Remote Request ------------------------------------------------------—

Notes:

  • Basic CAN: RTR is Bit 4 in TXDES1.
  • Peli CAN: RTR is Bit 6 in frameinfo.

◆ CAN_SELF_TEST_MODE

#define CAN_SELF_TEST_MODE   0x04

Self test mode

◆ CAN_SFF

#define CAN_SFF   0x00

standard fame format

◆ CAN_SFF_MASK

#define CAN_SFF_MASK   0x000007FFU

Standard Frame Format (SFF)

◆ CAN_SLEEP_MODE

#define CAN_SLEEP_MODE   0x10

Sleep Mode

◆ CAN_TIM0_1000K

#define CAN_TIM0_1000K   0

BTR0 value for timing of 1000 kHz

◆ CAN_TIM0_100K

#define CAN_TIM0_100K   4

BTR0 value for timing of 100 kHz

◆ CAN_TIM0_10K

#define CAN_TIM0_10K   49

BTR0 value for timing of 10 kHz

◆ CAN_TIM0_125K

#define CAN_TIM0_125K   3

BTR0 value for timing of 125 kHz

◆ CAN_TIM0_20K

#define CAN_TIM0_20K   24

BTR0 value for timing of 20 kHz

◆ CAN_TIM0_250K

#define CAN_TIM0_250K   1

BTR0 value for timing of 250 kHz

◆ CAN_TIM0_40K

#define CAN_TIM0_40K   0x89

BTR0 value for timing of 40 kHz

◆ CAN_TIM0_500K

#define CAN_TIM0_500K   0

BTR0 value for timing of 500 kHz

◆ CAN_TIM0_50K

#define CAN_TIM0_50K   9

BTR0 value for timing of 50 kHz

◆ CAN_TIM0_800K

#define CAN_TIM0_800K   0

BTR0 value for timing of 800 kHz

◆ CAN_TIM1_1000K

#define CAN_TIM1_1000K   0x14

BTR1 value for timing of 1000 kHz

◆ CAN_TIM1_100K

#define CAN_TIM1_100K   0x1c

BTR1 value for timing of 100 kHz

◆ CAN_TIM1_10K

#define CAN_TIM1_10K   0x1c

BTR1 value for timing of 10 kHz

◆ CAN_TIM1_125K

#define CAN_TIM1_125K   0x1c

BTR1 value for timing of 125 kHz

◆ CAN_TIM1_20K

#define CAN_TIM1_20K   0x1c

BTR1 value for timing of 20 kHz

◆ CAN_TIM1_250K

#define CAN_TIM1_250K   0x1c

BTR1 value for timing of 250 kHz

◆ CAN_TIM1_40K

#define CAN_TIM1_40K   0xEB

BTR1 value for timing of 40 kHz

◆ CAN_TIM1_500K

#define CAN_TIM1_500K   0x1c

BTR1 value for timing of 500 kHz

◆ CAN_TIM1_50K

#define CAN_TIM1_50K   0x1c

BTR1 value for timing of 50 kHz

◆ CAN_TIM1_800K

#define CAN_TIM1_800K   0x16

BTR1 value for timing of 800 kHz

◆ CAN_TRANSMISSION_COMPLETE_STATUS

#define CAN_TRANSMISSION_COMPLETE_STATUS   (1<<3)

bit 3 in Status Register (see include/can/sja1000.h for details)

◆ CAN_TRANSMISSION_REQUEST

#define CAN_TRANSMISSION_REQUEST   (1<<0)

bit 0 in Command Register (see include/can/sja1000.h for details)

◆ CAN_TRANSMIT_BUFFER_ACCESS

#define CAN_TRANSMIT_BUFFER_ACCESS   (1<<2)

bit 2 in Status Register (see include/can/sja1000.h for details)

◆ CAN_TRANSMIT_INT

#define CAN_TRANSMIT_INT   (1<<1)

bit 1 in Interrupt Register (see include/can/sja1000.h for details)

◆ CAN_TRANSMIT_INT_ENABLE

#define CAN_TRANSMIT_INT_ENABLE   (1<<1)

bit 1 in Interrupt Enable Register (see include/can/sja1000.h for details)

◆ CAN_TRANSMIT_STATUS

#define CAN_TRANSMIT_STATUS   (1<<5)

bit 5 in Status Register (see include/can/sja1000.h for details)

◆ CAN_WAKEUP_INT

#define CAN_WAKEUP_INT   (1<<4)

bit 4 in Interrupt Register (see include/can/sja1000.h for details)

◆ CAN_WAKEUP_INT_ENABLE

#define CAN_WAKEUP_INT_ENABLE   (1<<4)

bit 4 in Interrupt Enable Register (see include/can/sja1000.h for details)

◆ CANDRIVERERROR

#define CANDRIVERERROR   0xFFFFFFFFul

Invalid CAN ID == Error

◆ DBGprint

#define DBGprint (   ms,
  ar 
)    { }

Fancy leveled debugging not really needed in simpler QNX driver environment.

◆ MSG_ACTIVE

#define MSG_ACTIVE   (0)

Controller Error Active

◆ MSG_BASE

#define MSG_BASE   (0)

Base Frame Format

◆ MSG_BOVR

#define MSG_BOVR   (1<<7)

receive/transmit buffer overflow

◆ MSG_BUSOFF

#define MSG_BUSOFF   (1<<5)

controller Bus Off

◆ MSG_ERR_MASK

#define MSG_ERR_MASK   (MSG_OVR+MSG_PASSIVE+MSG_BUSOFF+MSG_BOVR+MSG_WARNING)

mask used for detecting CAN errors in the canmsg_t flags field

◆ MSG_EXT

#define MSG_EXT   (1<<2)

extended message format

◆ MSG_OVR

#define MSG_OVR   (1<<1)

CAN controller Msg overflow error

◆ MSG_PASSIVE

#define MSG_PASSIVE   (1<<4)

controller in error passive

◆ MSG_RTR

#define MSG_RTR   (1<<0)

RTR Message

◆ MSG_SELF

#define MSG_SELF   (1<<3)

message received from own tx

◆ MSG_WARNING

#define MSG_WARNING   (1<<6)

CAN Warning Level reached

◆ SJA1000_MAP_SIZE

#define SJA1000_MAP_SIZE   128

TODO

Typedef Documentation

◆ CanStatusPar_t

typedef struct CanStatusPar CanStatusPar_t

IOCTL generic CAN controller status request parameter structure

Function Documentation

◆ __attribute__()

struct canregs __attribute__ ( (packed)  )

PeliCAN address allocation for the CAN controller.

Each address denotes the location of a byte, whose elements are later described throughout this file. The addresses are in incrementing order starting from canmode (address=0) to canclk (address=31).

Variable Documentation

◆ arbitrationlost

BYTE arbitrationlost

11: arbitration lost capture only

◆ can_base_addr

canregs_t* can_base_addr

This must be initialized to the mapped address of the CAN channel.

◆ canclk

BYTE canclk

31: clock divider

◆ cancmd

BYTE cancmd

1: command register

◆ canirq

BYTE canirq

3: interrupt register

◆ canirq_enable

BYTE canirq_enable

4: interrupt enable register

◆ canmode

BYTE canmode

0: mode register

◆ canoutc

BYTE canoutc

8: output control register

◆ canrxbufferadr

BYTE canrxbufferadr

30: RX buffer start address (read only)

◆ canstat

BYTE canstat

2: status register

◆ cantest

BYTE cantest

9: command register

◆ cantim0

BYTE cantim0

6: bus timing 0 register

◆ cantim1

BYTE cantim1

7: bus timing 1 register

◆ errorcode

BYTE errorcode

12: error code capture (read only)

◆ errorwarninglimit

BYTE errorwarninglimit

13: error warning limit register

◆ frame

union frame frame

TODO

◆ frameinfo

BYTE frameinfo

TODO

◆ reserved1

BYTE reserved1

5: reserved register (read only)

◆ reserved2

BYTE reserved2

10: reserved register (read only)

◆ reserved3

BYTE reserved3

29: RX message counter (read only)

◆ rxerror

BYTE rxerror

14: RX error counter

◆ txerror

BYTE txerror

15: RX error counter

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