#include <sja1000.h>
Detailed Description
PeliCAN address allocation for the CAN controller.
Each address denotes the location of a byte, whose elements are later described throughout this file. The addresses are in incrementing order starting from canmode (address=0) to canclk (address=31).
Member Data Documentation
◆ arbitrationlost
| BYTE canregs::arbitrationlost |
11: arbitration lost capture only
◆ canclk
| BYTE canregs::canclk |
31: clock divider
◆ cancmd
| BYTE canregs::cancmd |
1: command register
◆ canirq
| BYTE canregs::canirq |
3: interrupt register
◆ canirq_enable
| BYTE canregs::canirq_enable |
4: interrupt enable register
◆ canmode
| BYTE canregs::canmode |
0: mode register
◆ canoutc
| BYTE canregs::canoutc |
8: output control register
◆ canrxbufferadr
| BYTE canregs::canrxbufferadr |
30: RX buffer start address (read only)
◆ canstat
| BYTE canregs::canstat |
2: status register
◆ cantest
| BYTE canregs::cantest |
9: command register
◆ cantim0
| BYTE canregs::cantim0 |
6: bus timing 0 register
◆ cantim1
| BYTE canregs::cantim1 |
7: bus timing 1 register
◆ errorcode
| BYTE canregs::errorcode |
12: error code capture (read only)
◆ errorwarninglimit
| BYTE canregs::errorwarninglimit |
13: error warning limit register
◆ frame
| union frame canregs::frame |
TODO
◆ frameinfo
| BYTE canregs::frameinfo |
TODO
◆ reserved1
| BYTE canregs::reserved1 |
5: reserved register (read only)
◆ reserved2
| BYTE canregs::reserved2 |
10: reserved register (read only)
◆ reserved3
| BYTE canregs::reserved3 |
29: RX message counter (read only)
◆ rxerror
| BYTE canregs::rxerror |
14: RX error counter
◆ txerror
| BYTE canregs::txerror |
15: RX error counter
The documentation for this struct was generated from the following file:
- include/can/sja1000.h
