sja1000.h

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#include <sys/time.h>
#include "utils/common.h"
#include "utils/timestamp.h"
#include "delay.h"              /* atomic_t */

#ifndef INCLUDE_CAN_SJA1000_H_
#define INCLUDE_CAN_SJA1000_H_

#define SJA1000_MAP_SIZE 128


/* --- Standard definition with offset 1 -------------------------------------*/

union frame {
    struct {
        BYTE canid1;        
        BYTE canid2;        
        BYTE canid3;        
        BYTE canid4;        
        BYTE canxdata[8];   
    } extframe;             
    struct {
        BYTE canid1;        
        BYTE canid2;        
        BYTE candata[8];    
    } stdframe;             
};

typedef struct canregs {
    BYTE canmode;           
    BYTE cancmd;            
    BYTE canstat;           
    BYTE canirq;            
    BYTE canirq_enable;     
    BYTE reserved1;         
    BYTE cantim0;           
    BYTE cantim1;           
    BYTE canoutc;           
    BYTE cantest;           
    BYTE reserved2;         
    BYTE arbitrationlost;   
    BYTE errorcode;         
    BYTE errorwarninglimit; 
    BYTE rxerror;           
    BYTE txerror;           
    BYTE frameinfo;         
    union frame frame;      
    BYTE reserved3;         
    BYTE canrxbufferadr;    
    BYTE canclk;            
} __attribute__((packed)) canregs_t;

#define CAN_RANGE 0x20      /* default: 32 registers */


/* --- Mode Register -----------------------------------------------------------
 *
 * The contents of the mode register are used to change the behavior of the CAN
 * controller. Bits may be set or reset by the CPU which uses the control
 * register as a read/write memory. Reserved bits are read as logic 0.
 *
 * Bit 0
 * -----
 *  0   normal; on the ‘1-to-0’ transition of the reset mode bit, the CAN
 *      controller returns to the operating mode
 *  1   reset; detection of a set reset mode bit results in aborting the current
 *      transmission/reception of a message and entering the reset mode
 *
 * Bit 1
 * -----
 *  0   normal
 *  1   listen only; in this mode the CAN controller would give no acknowledge
 *      to the CAN-bus, even if a message is received successfully; the error
 *      counters are stopped at the current value
 *
 * Bit 2
 * -----
 *  0   normal; an acknowledge is required for successful transmission
 *  1   self test; in this mode a full node test is possible without any other
 *      active node on the bus using the self reception request command; the CAN
 *      controller will perform a successful transmission, even if there is no
 *      acknowledge received
 *
 * Bit 3
 * -----
 *  0   dual; the dual acceptance filter option is enabled (two filters, each
 *      with the length of 16 bit are active)
 *  1   single; the single acceptance filter option is enabled (one filter with
 *      the length of 32 bit is active)
 *
 * Bit 4
 * -----
 *  0   wake-up; the CAN controller wakes up if sleeping
 *  1   sleep; the CAN controller enters sleep mode if no CAN interrupt
 *      is pending and if there is no bus activity
 */

#define CAN_SLEEP_MODE               0x10   
#define CAN_ACC_FILT_MASK            0x08   
#define CAN_SELF_TEST_MODE           0x04   
#define CAN_LISTEN_ONLY_MODE         0x02   
#define CAN_RESET_REQUEST            0x01   
#define CAN_MODE_DEF    CAN_ACC_FILT_MASK   
/* --- Interrupt Enable Register -----------------------------------------------
 *
 * The register allows to enable different types of interrupt sources which are
 * indicated to the CPU. A value of 0 implies that the interrupt is disabled,
 * while a value of 1 implies the interrupt is enabled.
 *
 * The interrupt enable register appears to the CPU as a read/write memory.
 *
 * Bit 0 : when the receive buffer status is 'full' the CAN controller requests
 *         the respective interrupt
 * Bit 1 : when a message has been successfully transmitted or the transmit
 *         buffer is accessible again (e.g. after an abort transmission
 *         command), the CAN controller requests the respective interrupt
 * Bit 2 : if the error or bus status change (see status register; Table 14),
 *         the CAN controller requests the respective interrupt
 * Bit 3 : if the data overrun status bit is set (see status register; Table
 *         14), the CAN controller requests the respective interrupt
 * Bit 4 : if the sleeping CAN controller wakes up, the respective interrupt is
 *         requested
 * Bit 5 : if the error status of the CAN controller changes from error active
 *         to error passive or vice versa, the respective interrupt is requested
 * Bit 6 : if the CAN controller has lost arbitration, the respective interrupt
 *         is requested
 * Bit 7 : if an bus error has been detected, the CAN controller requests the
 *         respective interrupt
 */

#define CAN_ERROR_BUSOFF_INT_ENABLE     (1<<7)  
#define CAN_ARBITR_LOST_INT_ENABLE      (1<<6)  
#define CAN_ERROR_PASSIVE_INT_ENABLE    (1<<5)  
#define CAN_WAKEUP_INT_ENABLE           (1<<4)  
#define CAN_OVERRUN_INT_ENABLE          (1<<3)  
#define CAN_ERROR_INT_ENABLE            (1<<2)  
#define CAN_TRANSMIT_INT_ENABLE         (1<<1)  
#define CAN_RECEIVE_INT_ENABLE          (1<<0)  
/* --- Frame information register ----------------------------------------------
 *
 * 0x00 : CAN message format = standard frame
 *
 *      Bits    1 : Denotes the start of frame transmission
 *      Bits   11 : A (unique) identifier which also represents the message
 *                  priority.
 *      Bits    1 : Must be dominant (0) for data frames and recessive (1) for
 *                  remote request frames (see Remote Frame, below).
 *      Bits    1 : Must be dominant (0) for base frame format with 11-bit
 *                  identifiers
 *      Bits    1 : Reserved bit. Must be dominant (0), but accepted as either
 *                  dominant or recessive.
 *      Bits    4 : Number of bytes of data (0–8 bytes)[a]
 *      Bits 0–64 : Data to be transmitted (length in bytes dictated by DLC
 *                  field)
 *      Bits   15 : Cyclic redundancy check
 *      Bits    1 : Must be recessive (1)
 *      Bits    1 : Transmitter sends recessive (1) and any receiver can assert
 *                  a dominant (0)
 *      Bits    1 : ACK delimiter, Must be recessive (1)
 *      Bits    7 : End-of-frame (EOF), Must be recessive (1)
 *
 * 0x80 : CAN message format = extended frame
 *
 *      Bits    1 : Denotes the start of frame transmission
 *      Bits   11 : First part of the (unique) identifier which also represents
 *                  the message priority.
 *      Bits    1 : Must be recessive (1)
 *      Bits    1 : Must be recessive (1) for extended frame format with 29-bit
 *                  identifiers.
 *      Bits   18 : Second part of the (unique) identifier which also represents
 *                  the message priority.
 *      Bits    1 : Must be dominant (0) for data frames and recessive (1) for
 *                  remote request frames (see Remote Frame, below).
 *      Bits    2 : Reserved bits which must be set dominant (0), but accepted
 *                  as either dominant or recessive
 *      Bits    4 : Number of bytes of data (0–8 bytes)[a]
 *      Bits 0–64 : Data to be transmitted (length dictated by DLC field)
 *      Bits   15 : Cyclic redundancy check
 *      Bits    1 : Must be recessive (1)
 *      Bits    1 : Transmitter sends recessive (1) and any receiver can assert
 *                  a dominant (0)
 *      Bits    1 : ACK delimiter, Must be recessive (1)
 *      Bits    7 : End-of-frame (EOF), Must be recessive (1)
 */

#define CAN_EFF     0x80    
#define CAN_SFF     0x00    
/* --- Command Register --------------------------------------------------------
 *
 * A command bit initiates an action within the transfer layer of the SJA1000.
 * The command register appears to the microcontroller as a write only memory.
 * If a read access is performed to this address the byte '11111111' is
 * returned. Between two commands at least one internal clock cycle is needed to
 * process. The internal clock is divided by two from the external oscillator
 * frequency.
 *
 * Note: For bits 0-3, if the value is set to 0, no action is performed.
 *
 * Bit 0 : If set to 0, no action is performed. If set to 1, a message will be
 *         transmitted.
 * Bit 1 : If set to 0, no action is performed. If set to 1, if not already in
 *         progress, a pending transmission request is cancelled.
 * Bit 2 : If set to 0, no action is performed. If set to 1, the receive buffer,
 *         representing the message memory space in the RXFIFO is released.
 * Bit 3 : If set to 0, no action is performed. If set to 1, the data overrun
 *         status bit is cleared.
 * Bit 4 : If set to 0, the SJA1000 wakes up, i.e. operates normally. If set to
 *         1, the SJA1000 enters sleep mode if no CAN interrupt is pending and
 *         there is no bus activity
 */

#define CAN_GOTO_SLEEP              (1<<4)  
#define CAN_CLEAR_OVERRUN_STATUS    (1<<3)  
#define CAN_RELEASE_RECEIVE_BUFFER  (1<<2)  
#define CAN_ABORT_TRANSMISSION      (1<<1)  
#define CAN_TRANSMISSION_REQUEST    (1<<0)  
/* --- Status Register ---------------------------------------------------------
 *
 * The content of the status register reflects the status of the SJA1000. The
 * status register appears to the microcontroller as a read only memory.
 *
 * Bit 0
 * -----
 *  0   empty; no message is available
 *  1   full; one or more messages are available in the RXFIFO
 *
 * Bit 1
 * -----
 *  0   absent; no data overrun has occurred since the last clear data overrun
 *      command was given
 *  1   overrun; a message was lost because there was not enough space for that
 *      message in the RXFIFO
 *
 * Bit 2
 * -----
 *  0   locked; the CPU cannot access the transmit buffer; a message is waiting
 *      for transmission or is already in process
 *  1   released; the CPU may write a message into the transmit buffer
 *
 * Bit 3
 * -----
 *  0   incomplete; the previously requested transmission is not yet completed
 *  1   complete; the last requested transmission has been successfully
 *      completed
 *
 * Bit 4
 * -----
 *  0   idle; no receive message is in progress
 *  1   receive; the SJA1000 is receiving a messages
 *
 * Bit 5
 * -----
 *  0   idle; no transmit message is in progress
 *  1   transmit; the SJA1000 is transmitting a message
 *
 * Bit 6
 * -----
 *  0   ok; both error counters are below the warning limit
 *  1   error; at least one of the error counters has reached or exceeded the
 *      CPU warning limit
 *
 * Bit 7
 * -----
 *  0   bus-on; the SJA1000 is involved in bus activities
 *  1   bus-off; the SJA1000 is not involved in bus activities
 */

#define CAN_BUS_STATUS                      (1<<7)  
#define CAN_ERROR_STATUS                    (1<<6)  
#define CAN_TRANSMIT_STATUS                 (1<<5)  
#define CAN_RECEIVE_STATUS                  (1<<4)  
#define CAN_TRANSMISSION_COMPLETE_STATUS    (1<<3)  
#define CAN_TRANSMIT_BUFFER_ACCESS          (1<<2)  
#define CAN_DATA_OVERRUN                    (1<<1)  
#define CAN_RECEIVE_BUFFER_STATUS           (1<<0)  
/* --- Interrupt Register ------------------------------------------------------
 *
 * Bit 0
 * -----
 *  0   reset; this bit is cleared by any read access of the microcontroller
 *  1   set; this bit is set while the receive FIFO is not empty and the receive
 *      interrupt enable bit is set to logic 1 (enabled)
 *
 * Bit 1
 * -----
 *  0   reset; this bit is cleared by any read access of the microcontroller
 *  1   set; this bit is set whenever the transmit buffer status changes from
 *      logic 0 to logic 1 (released) and transmit interrupt enable is set to
 *      logic 1 (enabled)
 *
 * Bit 2
 * -----
 *  0   reset; this bit is cleared by any read access of the microcontroller
 *  1   set; this bit is set on a change of either the error status or bus
 *      status bits if the error interrupt enable is set to logic 1 (enabled)
 *
 * Bit 3
 * -----
 *  0   reset; this bit is cleared by any read access of the microcontroller
 *  1   set; this bit is set on a ‘0-to-1’ transition of the data overrun status
 *      bit, when the data overrun interrupt enable is set to logic 1 (enabled)
 *
 * Bit 4
 * -----
 *  0   reset; this bit is cleared by any read access of the microcontroller
 *  1   set; this bit is set when the sleep mode is left
 */

#define CAN_WAKEUP_INT      (1<<4)  
#define CAN_OVERRUN_INT     (1<<3)  
#define CAN_ERROR_INT       (1<<2)  
#define CAN_TRANSMIT_INT    (1<<1)  
#define CAN_RECEIVE_INT     (1<<0)  
/* --- Output Control Register -------------------------------------------------
 *
 *  7       6       5       4       3       2       1       0
 *  OCTP1   OCTN1   OCPOL1  OCTP0   OCTN0   OCPOL0  OCMODE1 OCMODE0
 *  ----------------------  ----------------------  ---------------
 *  TX1 Output              TX0 Output              Programmable
 *  Driver Control          Driver Control          Output Functions
 *
 *  MODE
 *  OCMODE1 OCMODE0
 *  0       1       Normal Mode; TX0, TX1 bit sequence TXData
 *  1       1       Normal Mode; TX0 bit sequence, TX1 busclock TXCLK
 *  0       0       Biphase Mode
 *  1       0       Test Mode; TX0 bit sequence, TX1 COMPOUT
 *
 *  In normal Mode Voltage Output Levels depend on Driver Characteristic: OCTPx,
 *  OCTNx and programmed Output Polarity: OCPOLx
 *
 *  Driver Characteristic
 *  OCTPx   OCTNx
 *  0       0       always Floating Outputs,
 *  0       1       Pull Down
 *  1       0       Pull Up
 *  1       1       Push Pull
 */

#define CAN_OCTP1       (1<<7)  
#define CAN_OCTN1       (1<<6)  
#define CAN_OCPOL1      (1<<5)  
#define CAN_OCTP0       (1<<4)  
#define CAN_OCTN0       (1<<3)  
#define CAN_OCPOL0      (1<<2)  
#define CAN_OCMODE1     (1<<1)  
#define CAN_OCMODE0     (1<<0)  
/* --- Clock Divider Register --------------------------------------------------
 *
 * The clock divider register controls the CLKOUT frequency for the
 * microcontroller and allows to deactivate the CLKOUT pin. Additionally a
 * dedicated receive interrupt pulse on TX1, a receive comparator bypass and the
 * selection between BasicCAN mode and PeliCAN mode is made here. The default
 * state of the register after hardware reset is divide-by-12 for Motorola mode
 * (00000101) and divide-by-2 for Intel mode (00000000).
 *
 * On software reset (reset request/reset mode) this register is not influenced.
 *
 * The reserved bit (CDR.4) will always reflect a logic 0. The application
 * software should always write a logic 0 to this bit in order to be compatible
 * with future features, which may be 1-active using this bit.
 */

#define CAN_MODE_BASICCAN   (0x00)  
#define CAN_MODE_PELICAN    (0xC0)  
/* Original code from can4linux only used CAN_MODE_CLK, which was
 *  defined to the CAN_MODE_CLK1 value shown here. */
#define CAN_MODE_CLK1       (0x07)      
#define CAN_MODE_CLK2       (0x00)      
#define CAN_MODE_CLK        CAN_MODE_CLK2


# define CAN_RTR        (1<<6)


/* these timings are valid for clock 8Mhz */

#define CAN_TIM0_10K    49          
#define CAN_TIM1_10K    0x1c        
#define CAN_TIM0_20K    24          
#define CAN_TIM1_20K    0x1c        
#define CAN_TIM0_40K    0x89        
#define CAN_TIM1_40K    0xEB        
#define CAN_TIM0_50K    9           
#define CAN_TIM1_50K    0x1c        
#define CAN_TIM0_100K   4           
#define CAN_TIM1_100K   0x1c        
#define CAN_TIM0_125K   3           
#define CAN_TIM1_125K   0x1c        
#define CAN_TIM0_250K   1           
#define CAN_TIM1_250K   0x1c        
#define CAN_TIM0_500K   0           
#define CAN_TIM1_500K   0x1c        
#define CAN_TIM0_800K   0           
#define CAN_TIM1_800K   0x16        
#define CAN_TIM0_1000K  0           
#define CAN_TIM1_1000K  0x14        
/* External structures may not be used, declared in can_dev.c for compatibility
 * with can4linux sja1000.cpp.
 *
 * For PATH driver, each channel has a separate driver, so MAX_CHANNELS is 1
 */
#define MAX_CHANNELS    1
#define MY_CHANNEL      0

#define DBGprint(ms,ar) { }
#define DBGin() { }
#define DBGout()        { }
#define DEBUG_TTY(n, args...)
extern unsigned int dbgMask;

typedef struct CanStatusPar {
    unsigned int baud;                  
    unsigned int status;                
    unsigned int error_warning_limit;   
    unsigned int rx_errors;             
    unsigned int tx_errors;             
    unsigned int error_code;            
    unsigned int rx_buffer_size;        
    unsigned int rx_buffer_used;        
    unsigned int tx_buffer_size;        
    unsigned int tx_buffer_used;        
    unsigned long retval;               
} CanStatusPar_t;

struct inode {
    int dummy;
};

struct _instance_data {
    int rx_index;
};

struct file {
    void *private_data;
};

#define MSG_ACTIVE      (0)             
#define MSG_BASE        (0)             
#define MSG_RTR         (1<<0)          
#define MSG_OVR         (1<<1)          
#define MSG_EXT         (1<<2)          
#define MSG_SELF        (1<<3)          
#define MSG_PASSIVE     (1<<4)          
#define MSG_BUSOFF      (1<<5)          
#define MSG_WARNING     (1<<6)          
#define MSG_BOVR        (1<<7)          
#define MSG_ERR_MASK    (MSG_OVR+MSG_PASSIVE+MSG_BUSOFF+MSG_BOVR+MSG_WARNING)

/* valid bits in CAN ID for frame formats */
#define CAN_SFF_MASK    0x000007FFU     
#define CAN_EFF_MASK    0x1FFFFFFFU     
#define CANDRIVERERROR  0xFFFFFFFFul    
/* Bogus definitions to get simplest case to make Linux ISR in sja1000.cpp
 * compile -- not used. */
#define LINUX_VERSION_CODE      1
#define KERNEL_VERSION(X,Y,Z)   0
typedef int irqreturn_t;
#define IRQ_NONE                0
#define IRQ_HANDLED             1
#define IRQ_RETVAL(x)           (x)


/* -------------------------------------------------------------------------- */
/* -------------------- Imported from sja1000/can_dev.h --------------------- */
/* -------------------------------------------------------------------------- */

extern canregs_t *can_base_addr;

static inline unsigned char can_read_reg(BYTE *addr)
{
    volatile BYTE *preg = (volatile BYTE*) (addr);
    return *preg;
}

static inline void can_write_reg(BYTE *addr, BYTE value)
{
    volatile BYTE *preg = (volatile BYTE*) (addr);
    *preg = value;
}

static inline void can_set_reg(BYTE *addr, BYTE mask)
{
    volatile BYTE *preg = (volatile BYTE*) (addr);
    *preg |= mask;
}

static inline void can_reset_reg(BYTE *addr, BYTE mask)
{
    volatile BYTE *preg = (volatile BYTE *) (addr);
    *preg &= ~(mask);
}

/* Board access macros, as used in can4linux, rely on a packed structure for
 * canregs_t that mirrors the offsets of the actual registers.
 *
 * Unlike can4linux, each instance of the can_man resource manager corresponds
 * to one SJA 1000 chip and one CAN port. Unused bd (board) parameter to macros
 * is retained for compatibility in sja1000.cpp.
 */
#define CANin(bd,adr) can_read_reg(&can_base_addr->adr)
#define CANout(bd,adr,v) can_write_reg(&can_base_addr->adr, v)
#define CANset(bd,adr,m) can_set_reg(&can_base_addr->adr, m)
#define CANreset(bd,adr,m) can_reset_reg(&can_base_addr->adr, m)


#ifdef CPC_PCI
#define R_OFF 4 /* offset 4 for the EMS CPC-PCI card */
#else
#define R_OFF 1
#endif

#endif /* INCLUDE_CAN_SJA1000_H_ */